Miért lett a cachek (gyorsítótárak) neve L1, L2, L3?

Level 1,Level 2,Level 3

Elsődleges,Másodlagos,Harmadlagos.

L1 cache is physically next to the processing core and is implemented in SRAM, or Static RAM which is fast and constant when powered on. It does not require refresh cycles. It is generally split with half used for instruction code and the the other used for data.

L2 cache is physically close to the core, but is implemented in DRAM or Dynamic RAM and goes through refresh cycles many time a second to retain its memory. It is not as fast as L1 and cannot be accessed during refresh.

L3 cache has come into vogue with the advent of multi-core CPUs. Whereas these chips will have both L1 and L2 caches for each separate core; there is a common fairly large L3 shared by all cores. It is usually the size of all other caches combined or a few multiples of all other caches combined. It is also implemented in DRAM. One unusual thing is that a multi-core chip that is running software that may not be capable of or need all cores will have a core flush its caches into the L3 before that core goes dormant.

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